Introduction to Analog Integrated Circuit Layout
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30 June – 4 July 2025
- FEE CTU in Prague

Are you ready to level up your skills in analog integrated circuit (IC) layout? Apply now for our one-week, on-site summer school held at the Faculty of Electrical Engineering, Czech Technical University in Prague. The practical exercises are led by Prof. Dr. Poki Chen (NTUST) and they will take place in the Cadence computer laboratory at the Faculty of Electrical Engineering of the Czech Technical University in Prague.
Integrated circuits (ICs) are essential components in almost all modern commercial products worldwide, making semiconductors a top strategic industry for many nations. As a result, engineers in this field consistently earn significantly higher wages than average.
Students pursuing a career in analog IC engineering must master two fundamental courses: Analog IC Design and Analog IC Layout. This intensive course is designed to familiarize students with the evolution of the IC industry while equipping them with essential knowledge and practical skills in analog IC layout. It serves as a continuation of the course offered last summer.
To enhance learning, students will work on the layout of an exemplified two-stage operational amplifier (OPAMP), incorporating a resistor and a capacitor for negative feedback. They will know not only how to do but also the reasons why. This hands-on experience will deepen their understanding of analog IC layout, preparing them for future studies and successful careers in the rapidly advancing Fourth Industrial Revolution.
Course Outlines:
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Monday
June 30, 2025
Morning:
Brief history about semiconductor evolution
Introduction to integrated circuit design/layout flow
Comparison between 2D MOSFET and 3D FinFET layoutsAfternoon:
Cadence/Synopsis environment
Symbol, schematic and layout views
Result exports -
Tuesday
July 1, 2025
Morning:
Introduction to integrated circuit manufacturing
Mismatches versus strategiesAfternoon:
First-order common-centroid layout of simple current mirror
DRC & LVS
Pre-simulation versus post-simulation -
Wednesday
July 2, 2025
Morning:
Introduction to layout of transistors
Dummy and guard ring of transistors
Matching of transistor layoutAfternoon:
Second-order common-centroid layout of differential pair
Differential amplifier layout -
Thursday
July 3, 2025
Morning:
Types of on-chip resistors
Dummy and guard ring of resistors
Matching of resistor layoutAfternoon:
High-gain stage layout
Polysilicon resistor layout with dummy and guard ring -
Friday
July 4, 2025
Morning:
Types of on-chip capacitors
Dummy and guard ring of capacitors
Matching of capacitor layoutAfternoon:
Layout of metal-insulator-metal (MIM) capacitor
Layout of two-stage operational amplifier which combines all layout blocks of the week
FAQ
How much does it cost?
The summer school is free of charge.
I am a student. Will I get any ECTS?
FEE students will get 1 credit.
What is the teaching format of the course?
2 blocks of practical exercises.
Where will the practical exercises take place?
In the Cadence computer laboratory at the Faculty of Electrical Engineering - Czech technical university in Prague.
Where can I get accomodation in Prague?
You can stay in the Masaryk Dormitory near the faculty.
In what language will the summer school be held?
In English.
The capacity of the summer school is limited. We recommend to register as soon as possible.
This workshop is organised in the frame of The Advanced Chip Design Research Center (ACDRC), which aims to foster innovation and collaboration in semiconductor research and education between Taiwan and the Czech Republic. ACDRC is established under the Taiwan-Czech Democratic Partners Supply Chain Resilience and Capacity Building Cooperation Plan for 2022-2026. The center is dedicated to cultivating integrated circuit design talent across various fields and fostering the development of the semiconductor industry ecosystem in the Czech Republic.
You can find recordings of ACDRC workshops on our Youtube channel.
This project is a collaborative effort between Taiwanese and Czech organizations, specifically NARLabs and CyberSecurityHubcz, which serves as the main execution unit, complemented by a consortium that includes the Czech Technical University, Masaryk University and Brno University of Technology.
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